1. Field of the Invention
The invention relates to an analog to digital converting apparatus, and particularly relates to a successive approximation register analog to digital converting apparatus.
2. Description of Related Art
In the recent trends of integrated circuit design, the demands for lower power consumption, higher performance, and lower cost are more and more strict. In the design of an analog front-end circuit, an efficient analog to digital converter (ADC) can significantly improve the overall performance of the system.
There are several different frameworks of ADC, such as flash ADC, pipeline ADC, successive approximation register ADC (SAR-ADC), and two-step ADC. These ADC frameworks respectively have suitable conditions. When the requirements on specification remain the same, SAR-ADC has the advantage of lower power consumption and smaller chip area over the pipeline ADC. Thus, the development on SAR-ADC has gradually been valued in relevant industries.
The current framework of SAR-ADC usually includes an analog buffer for generating a common mode voltage. However, when the converting precision and frequency of SAR-ADC are higher, the power of the analog buffer may significantly increase, making the circuit design more difficult.